module cpu_top
(
	input wire sys_clk,
	input wire sys_rst_n,
	
	output wire [15:0] test_ip,
	output wire [15:0] test_instruct
);

wire init_done;
wire get_inst_en;
wire [15:0] instruct_pointer;
wire decode_en;
wire [15:0] instruct_word;
wire decode_done;
wire [4:0] op_code;
wire [2:0] reserve_bit;
wire [7:0] op_rand;

assign test_ip = instruct_pointer;
assign test_instruct = instruct_word;

sys_init sys_init_inst
(
	.sys_clk(sys_clk),
	.sys_rst_n(sys_rst_n),
	.init_done(init_done)
);

ctrl_center ctrl_center_inst
(
	.sys_clk(sys_clk),
	.sys_rst_n(sys_rst_n),
	.init_done(init_done),
	.decode_done(decode_done),
	.op_code_in(op_code),
	.reserve_bit_in(reserve_bit),
	.op_rand_in(op_rand),	
	.ip(instruct_pointer),	//instruction pointer
	.get_inst_en(get_inst_en)
);

get_instruct get_instruct_inst
(
	.sys_clk(sys_clk),
	.sys_rst_n(sys_rst_n),
	.get_inst_en(get_inst_en),
	.ip(instruct_pointer),
	.decode_en(decode_en),
	.instruct_code(instruct_word)
);

decode_unit decode_unit_inst
(
	.sys_clk(sys_clk),
	.sys_rst_n(sys_rst_n),
	.decode_en(decode_en),
	.instruct_word(instruct_word),
	.decode_done(decode_done),
	.op_code(op_code),
	.reserve_bit(reserve_bit),
	.op_rand(op_rand)
);

endmodule